The present invention relates to a method of manufacturing a semiconductor device such as an integrated circuit, particularly, to a technique useful for forming an electrode.
In the manufacture of a semiconductor device such as a semiconductor integrated circuit, various treatments such as a film-forming treatment, an etching treatment, and a doping treatment are performed repeatedly to form desired circuit elements on a substrate. When it comes to, for example, an MOS type semiconductor device, source and drain regions are formed by applying a doping treatment to desired surface regions of a silicon substrate to form diffusion layers. Further, for electrically connecting these diffusion layers to wiring layers, an interlayer insulating film covering these source and drain regions are selectively etched to form contact holes, followed by embedding a metal in these contact holes by a film-forming technique.
For improving the characteristics of a semiconductor integrated circuit, it is necessary to lower the sheet resistance of each of the diffusion layers forming the source and drain regions and the gate electrode. A so-called silicide technique, which is intended to lower the sheet resistance, is disclosed in, for example, Japanese Patent Disclosure (Kokai) No. 58-58766. It is disclosed that, after formation of the gate, source and drain regions, the entire surface of a silicon semiconductor substrate is covered with a metal layer having a high melting point, followed by applying an annealing treatment to convert only those portions of the metal layer which cover the gate, source and drain regions into silicide layers. Then, the unreacted metal layer is removed by a selective etching.
The silicide technique includes, for example, a titanium silicide technique in which a TiSi.sub.2 film is formed by self-alignment on the source and drain regions and on the gate electrode in order to lower the sheet resistance on any of the gate electrode and source and drain regions. In the titanium silicide technique, a Ti layer is formed first to cover the entire substrate surface by a sputtering method, followed by annealing the Ti layer at about 650.degree. C. under a nitrogen gas atmosphere. In this step, the part of the Ti layer in direct contact with silicon, i.e., in direct contact with each of the source and drain regions and the gate electrode, carries out reaction with silicon to form a TiSi.sub.2 layer. What should be noted, however, is that the TiSi.sub.2 layer thus formed has a C49 crystal phase having a relatively high resistivity, not a C54 crystal phase having a low resistivity.
In the next step, the unreacted Ti layer is removed by a selective etching, followed by applying a second annealing treatment to the substrate at a high temperature of about 800.degree. C. so as to convert the C49 crystal phase of TiSi.sub.2 into the C54 crystal phase having a low resistivity. If a Ti layer formed on an SiO.sub.2 insulating film is heated to 800.degree. C. or more, the metal Ti reacts with SiO.sub.2, making it difficult to remove the unreacted metal Ti in the subsequent step by a selective etching. To avoid this difficulty, the second annealing treatment is applied after removal of the metal Ti by the selective etching.
The conventional titanium silicide technique outlined above necessitates complex treatments and, thus, involves as many as 4 steps including the final step of the second annealing treatment, leading to a high manufacturing cost of the semiconductor device.
Measures for overcoming the above-noted difficulties are proposed in, for example, Japanese Patent Disclosures Nos. 8-97294 and 7-29713. It is proposed to form a Ti layer by a plasma CVD utilizing an electron cyclotron resonance (ECR), which uses a micro wave, or by a plasma CVD utilizing a helicon wave. This technique permits a Ti layer in direct contact with silicon to perform reaction with silicon so as to form directly a TiSi.sub.2 layer of the C54 crystal phase having a low resistivity without requiring an annealing treatment. However, it is necessary to use a plasma film-forming apparatus of complex structure. In addition, the TiSi.sub.2 layer formed by reaction of the deposited Ti with a silicon layer including a polycrystalline silicon layer is very thin relative to a Ti layer formed on an insulating film such as an SiO.sub.2 film, though the TiSi.sub.2 layer is certainly thicker than the Ti layer. Specifically, a ratio in thickness of the TiSi.sub.2 layer to the Ti layer is only about 2. As a result, a considerably large proportion of the TiSi.sub.2 layer is etched away in the subsequent step of removing the Ti layer by a selective etching. The etching of the TiSi.sub.2 layer results in failure to lower sufficiently the sheet resistance of the diffusion layer, though the particular technique certainly permits decreasing the number of process steps. Since it is required nowadays to achieve further miniaturization by improving the density and degree of integration of a semiconductor integrated circuit, it is strongly required to develop a technique which permits forming a diffusion layer of a low resistivity while decreasing the number of required process steps and, thus, suppressing the manufacturing cost.